Deep trench capacitors are formed on semiconductor devices using multi-step manufacturing processes. The details of manufacturing strongly depend on the use intended for the capacitors, but generally employ the following steps. First, a trench is formed in a silicon substrate. The side walls of the trench are lined with a dielectric material, and the trench is then filled with a conductive material, e.g., a metal. The substrate acts as one plate of the capacitor, and the conductive material acts as the second plate.
Currently, semiconductor devices are being constructed that are capable of performing several different functions, each potentially operating at different speeds and requiring different RC constants of the capacitors. Thus, sometimes it is desirable to form capacitors on a substrate, where the capacitors have two or more different capacitance levels.
Where dielectric thickness of two capacitors is the same, trench size and/or morphology can have an effect on the capacitances. In semiconductor devices, it may be desirable to achieve different capacitances using the same deep trench process. For example, on a microprocessor chip, a level 2 cache of fast embedded DRAM requires smaller RC constant than a level 3 cache, which demands longer retention time and thus higher deep trench capacitance.
The capacitances of trench capacitors are affected by numerous factors, including, among others, the surface areas and morphologies of the trench bottom and sidewalls, and the type and amount of dielectric material. Accordingly, there is a need in the industry to efficiently construct a semiconductor device capable of safely accommodating capacitors of various capacitances, while maintaining a small overall device size.
One method, for example, involves formation of trench capacitors having differing dielectric thickness. This process includes, among other things, formation of trenches of differing surface area, application of a dielectric material, removal of a portion of the first dielectric material, and application of a second dielectric material. The method requires use of more than one photolithography step, which increases manufacturing cost and complexity.
Thus, current methods for manufacturing capacitors for differing capacitance and/or voltage rating require extra masks, and/or additional process steps, each of which adds to the complexity and cost of manufacture. Further, each extra mask or step increases the possibility of a flaw being introduced into the chip.